Verilog netlist manipulations begin

I posted the 1st (re-written) version of the nldb project to: http://nldb.sourceforge.net.
As I had last mentioned at my other (related) project: http://v2kparse.blogspot.com, I realized a need (and opportunity) to solve an immediate issue, so re-architected nldb to use Java and Ruby.

The first use I found was to indentify and remove unreachable flip-flops from a netlist. There is a simple example in the download:

1) download release: nldb-1.0.tar.gz
2) unload and install
  mkdir nldb
   cd nldb
   tar zxvf ../nldb-1.0.tar.gz
3) make sure you have a java JRE and jruby installed:
  java -version
      java version "1.6.0_11"
      Java(TM) SE Runtime Environment (build 1.6.0_11-b03)
      Java HotSpot(TM) 64-Bit Server VM (build 11.0-b16, mixed mode)
  jruby -v
      jruby 1.2.0 (ruby 1.8.6 patchlevel 287) (2009-03-16 rev 9419) [amd64-java]
4) run the testcase (which is based on a Xilinx generated netlist):
  cd tests/t2
   ../../bin/nldb unreach --lib xlnx.lib.gv unreach.xlnx.gv
      Info: xlnx.lib.gv: processed (as a library) in 0 (secs).
      Info: unreach.xlnx.gv: processed in 0 (secs).
      Info: linking references ...
      Info: link (references) time: 0 (secs).
      Info: linking connections ...
      Info: link (connections) time: 0 (secs).
      Info: 0 (secs): total elapsed.
      Info: Unreachable pass 1 ...
      Info: unrch_d1_2_3: unreachable (deleted)
      Info: unrch_d1_2_2: unreachable (deleted)
      Info: unrch_d1_2_1: unreachable (deleted)
      Info: unrch_d1_2_0: unreachable (deleted)
      Info: Unreachable pass 2 ...
      Info: unrch_d1_1_0: unreachable (deleted)
      Info: unrch_d1_1_2: unreachable (deleted)
      Info: unrch_d1_1_1: unreachable (deleted)
      Info: unrch_d1_1_3: unreachable (deleted)
      Info: Unreachable pass 3 ...
      Info: After pass 1: 4 unreachable cell(s) deleted
      Info: After pass 2: 4 unreachable cell(s) deleted
      Info: 8 unreachable cell(s) deleted
      Info: unreach.save.gv: generating ...

NOTE: While I did use Xilinx ISE to generate a netlist from Verilog RTL (see tests/t2/unreach.v), be advised that the Xilinx synthesis tool does normally remove unreachable logic automatically (by default).

I coerced the tool to retain unreachable flops by embedding KEEP meta-comments in the RTL.

If I did not add the KEEP, the generated netlist would have removed the unreachables; and, this nldb example would not have been very interesting...

(Phew, hopefully that disclaimer will keep the Xilinx fans and lawyers from accusing me of spreading FUD!)

Now, in my normal day job, I synthesize for ASIC implementation (not FPGAs, currently). The ASIC synthesis tools often generated netlists w/ unreachable logic. Most times, it is a user/flow issue: i.e., there are dont-touches, desire for simpler FEC (formal equivalency checking), constraints, etc.

For whatever reason, my need was simply to find out any unreachables and then delete them. As is stated in the usage of my example:

#from tests/t2 directory
../../bin/nldb
  ...
  The unreachable algorithm repeatedly removes any unreachable flops until there
  are no more unreachable flops remaining.  This *repeat* operation is required,
  since there may be "pipelines" which are ultimately unreachable.

  A side-effect of removing (only) the unreachable flops could yield orphan
  (combinational) logic (which formerly fed into the now removed unreachable
  flops).  A future enhancement (or your own ruby code!) could add that
  enhancement.

So, that's all for now.
Enjoy!